Specifies the compressed trace architecture that captures instruction execution with minimal bandwidth overhead. This is the core trace format specification for RISC-V, enabling powerful profiling, debugging, and performance analysis workflows.

Defines the register-level interface for controlling shared resource capacity and bandwidth on RISC-V platforms. The specification allows software to assign quality-of-service attributes to workloads, improving predictability in mixed-criticality systems.

Specifies how reliability, availability, and serviceability (RAS) error records are structured and accessed on RISC-V hardware. RERI gives firmware and operating systems a standardized mechanism to detect, log, and respond to hardware faults.

Defines the external debug interfaces for RISC-V processors, covering the Debug Module, abstract commands, and hardware trigger mechanisms. This specification is essential for anyone building or integrating RISC-V debug probes and tooling.

Specifies the encapsulation format used to package raw trace data emitted by RISC-V hardware. This layer sits between the trace source and transport infrastructure, ensuring consistent framing regardless of the trace type.

Defines Nexus-based trace data formatting and transport for RISC-V. N-Trace provides an alternative to the E-Trace format, offering compatibility with industry-standard Nexus trace infrastructure widely used in embedded development environments.

Specifies the physical and logical connector definitions for RISC-V trace interoperability. This specification allows tooling vendors and hardware designers to produce probe and connector hardware that works consistently across RISC-V implementations.

Defines the software-visible control and configuration interface for RISC-V trace features. The TCI allows system software to start, stop, and configure trace sessions in a standardized way, independent of the underlying trace architecture.